Languages and Compilers for Parallel Computing : 18th International Workshop, LCPC 2005, Hawthorne, NY, USA, October 20-22, 2005, Revised Selected Papers - neues Buch

EAN (ISBN-13): 9783540693307
Erscheinungsjahr: 2005
Herausgeber: Springer Science+Business Media

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ISBN/EAN: 9783540693307

ISBN - alternative Schreibweisen:
978-3-540-69330-7
Alternative Schreibweisen und verwandte Suchbegriffe:
Autor des Buches: baumgartner, ramanujam, schueller
Titel des Buches: parallel computing

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Daten vom Verlag:

Autor/in: Eduard Ayguadé; Gerald Baumgartner; J. Ramanujam; P. Sadayappan
Titel: Theoretical Computer Science and General Issues; Lecture Notes in Computer Science; Languages and Compilers for Parallel Computing - 18th International Workshop, LCPC 2005, Hawthorne, NY, USA, October 20-22, 2005, Revised Selected Papers
Verlag: Springer; Springer Berlin
480 Seiten
Erscheinungsjahr: 2007-05-16
Berlin; Heidelberg; DE
Sprache: Englisch
53,49 € (DE)
55,00 € (AT)
59,00 CHF (CH)
Available
XII, 480 p.

EA; E107; eBook; Nonbooks, PBS / Informatik, EDV/Programmiersprachen; Compiler und Übersetzer; Verstehen; Compiler; Java; Monitor; Scheduling; Scheme; algorithm; algorithms; compiler optimization; compilers; concurrency; distributed memory systems; distributed systems; garbage collection; high performance computing; optimization; data structures; C; Compilers and Interpreters; Programming Techniques; Theory of Computation; Computer Communication Networks; Arithmetic and Logic Structures; Data Science; Computer Science; Computerprogrammierung und Softwareentwicklung; Theoretische Informatik; Netzwerk-Hardware; Computerhardware; Datenbanken; BC

Revisiting Graph Coloring Register Allocation: A Study of the Chaitin-Briggs and Callahan-Koblenz Algorithms.- Register Pressure in Software-Pipelined Loop Nests: Fast Computation and Impact on Architecture Design.- Manipulating MAXLIVE for Spill-Free Register Allocation.- Optimizing Packet Accesses for a Domain Specific Language on Network Processors.- Array Replication to Increase Parallelism in Applications Mapped to Configurable Architectures.- Generation of Control and Data Flow Graphs from Scheduled and Pipelined Assembly Code.- Applying Data Copy to Improve Memory Performance of General Array Computations.- A Cache-Conscious Profitability Model for Empirical Tuning of Loop Fusion.- Optimizing Matrix Multiplication with a Classifier Learning System.- A Language for the Compact Representation of Multiple Program Versions.- Efficient Computation of May-Happen-in-Parallel Information for Concurrent Java Programs.- Evaluating the Impact of Thread Escape Analysis on a Memory Consistency Model-Aware Compiler.- Concurrency Analysis for Parallel Programs with Textually Aligned Barriers.- Titanium Performance and Potential: An NPB Experimental Study.- Efficient Search-Space Pruning for Integrated Fusion and Tiling Transformations.- Automatic Measurement of Instruction Cache Capacity.- Combined ILP and Register Tiling: Analytical Model and Optimization Framework.- Analytic Models and Empirical Search: A Hybrid Approach to Code Optimization.- Testing Speculative Work in a Lazy/Eager Parallel Functional Language.- Loop Selection for Thread-Level Speculation.- Software Thread Level Speculation for the Java Language and Virtual Machine Environment.- Lightweight Monitoring of the Progress of Remotely Executing Computations.- Using Platform-Specific Performance Counters for Dynamic Compilation.- A Domain-Specific Interpreter for Parallelizing a Large Mixed-Language Visualisation Application.- Compiler Control Power Saving Scheme for Multi Core Processors.- Code Transformations for One-Pass Analysis.- Scalable Array SSA and Array Data Flow Analysis.- Interprocedural Symbolic Range Propagation for Optimizing Compilers.- Parallelization of Utility Programs Based on Behavior Phase Analysis.- A Systematic Approach to Model-Guided Empirical Search for Memory Hierarchy Optimization.- An Efficient Approach for Self-scheduling Parallel Loops on Multiprogrammed Parallel Computers.- Dynamic Compilation for Reducing Energy Consumption of I/O-Intensive Applications.- Supporting SELL for High-Performance Computing.- Compiler Supports and Optimizations for PAC VLIW DSP Processors.